Linearity and Mobility Degradation in Strained Si MOSFETs with Thin Gate Dielectrics

As gate dielectrics are scaled to a few atomic layers and the channel doping is increased to mitigate short channel effects, high vertical electric fields cause considerable mobility degradation through surface roughness scattering in silicon MOSFETs. This high field mobility degradation is known to influence the harmonic distortion through higher order drain current derivatives. Failure to take these higher order derivatives into account can cause significant error in the predictive evaluation of linearity (VIP3) in MOSFETs. Electrical measurements are used to extract the 2 order mobility degradation factor (θ2) from strained silicon MOSFETs with different germanium contents. Linearity and high-field mobility degradation are shown to be independent of strain in spite of atomic force microscopy measurements showing that the surface roughness root-meansquare amplitude increases with the germanium content. It is also shown that θ2 is required for the accurate modelling of linearity. The impact of oxide thickness on linearity is also investigated through θ2. In this paper, an analytical relationship between θ2 and the effective oxide thickness is developed and validated by electrical measurements on MOSFETs with different oxide thicknesses and θ2 values from the literature. Using the extracted θ2 values as inputs to analytical MOSFET models, a correlation between the oxide thickness and linearity is analyzed. Index Terms – Distortion, Linearity, Mobility degradation, Strained Silicon. INTRODUCTION The miniaturization of the metal oxide on semiconductor field effect transistor (MOSFET) has made complimentary metal oxide on semiconductor (CMOS) devices considerable radio frequency (RF) contenders where bipolars and high-electronmobility-transistors are traditionally dominant [1, 2]. Strain engineering in deep submicrometer CMOS devices has further improved the high speed performance required for RF implementation [3]. However in analog/mixed-signal applications, other metrics like noise and linearity are important [4-6]. Linearity is particularly of interest in CMOS devices since MOSFETs exhibit better linearity than bipolars [2]. In a perfectly linear MOSFET, a signal with a single harmonic at the input would yield an output signal at the same frequency. However, since MOSFETs are not perfectly linear, the output signal usually contains higher order harmonics that may interfere with the fundamental. These higher order harmonics are related to the higher order derivatives of the drain current with respect the terminal voltages according to n GS n GS m n GS GS m GS GS m GS m DS v v g v v g v v g v g i 1 1 3 2 2 2 ......... − − ∂ ∂ + ∂ ∂ + ∂ ∂ + ≈ (1) where DS i is the drain-source current, m g is the transconductance and GS v is the small signal gate-source voltage. Distortion analysis is important for analog MOSFETs since higher order harmonics at the output can cause interference with fundamental harmonic thereby resulting in inter-modulation distortion and degrading the signal integrity of the system. Of the higher order harmonics, the most important is the 3 order harmonic due to the fact that a signal close in frequency to the fundamental signal at the input of a MOSFET will have a third order intermodulation harmonic at the output of the MOSFET that will be close in frequency to the fundamental. Various figures of merit have been developed to quantify the linearity of RF transistors. The third order intercept point (IP3) is defined as the input power level at which the fundamental harmonic and the third order harmonic have equal power levels at the output. This is usually determined from extrapolations of RF power measurements. Another indicator of linearity is the VIP3 which is defined as the extrapolated gate voltage (VGS) bias at which the amplitudes of the 1 and 3 order derivatives of IDS are equal [2, 7-11]. The VIP3 can be measured from MOSFET DC IDS vs. VGS characteristics and is given by